The invention relates to a system for creating a datapath circuit layout, and more particularly to a system for creating layouts of datapath circuits for achieving a separation layout of a datapath section from a peripheral circuit.
The datapath circuits for microprocessors will be described prior to descriptions of a conventional datapath circuit layout creation system. FIGS. 1A to 1C illustrate configurations of datapath circuits. The datapath circuits include a plurality of datapath sections 110-1, 110-2, 110-3 and 110-4 and terminals 120-1, 120-2 and 120-3 in which individual datapath sections are connected to each other through connection paths. Each of the datapath sections includes a plurality of cells or datapath section cells 111-1, 111-2 and a plurality of peripheral circuits 112-1 and 112-2 as illustrated in FIG. 1B. The datapath section cells are connected to each other through connection paths. The datapath section cell includes one of arithmetic units such as arithmetic logic unit (ALU), a resist, a multiplexer and a buffer, while the peripheral circuit is provided for input/output of signals into and from the datapath section cell. The peripheral circuit may comprise a plurality of standard cells such as inventor and logic gates. The datapath section cell corresponds to a resistor transfer (RT) level. The datapath circuit may be called as a resistor transfer circuit or (RT circuit).
The description will be back to the datapath circuit layout creation system. FIG. 2A illustrates a layout 200 of the datapath circuit as a result of the automatic layout by the conventional datapath circuit layout creation system in which the datapath circuit does not include any control system for controlling operations of the datapath circuits. FIG. 2B illustrates a layout 200a of the datapath circuit as a result of the automatic layout by the conventional datapath circuit layout creation system in which the datapath circuit includes a control system 115 for controlling operations of the datapath circuits. From FIGS. 2A and 2B, the layout was made to separate the datapath sections 110 from the peripheral circuits 112 or from peripheral circuits/control systems 115.
Processes for automatic layout design by use of the conventional datapath circuit layout creation system and structures thereof will be described with reference to FIG. 3. The datapath circuit layout creation system includes a RT circuit diagram input section la into which a RT circuit diagram 100 of the datapath circuit is inputted. The system also includes a peripheral circuit/control system netlist file 20a for storing a peripheral circuit/control system netlist including information of the peripheral circuit and the control system as well as interconnections between them wherein the netlist was created with referring to the RT circuit diagram 100. The system also has a datapath section cell library 5 for storing data including informations of configurations, structures and interconnections of a plurality of the datapath section cells having the RT levels and involved in the RT circuit diagrams. The system also has a standard cell library for storing data including information of configurations, structures and interconnections of a plurality of the standard cells involved in the datapath circuit to construct the peripheral circuit and the control system. The system also has a library reference section 7a for referring to the datapath section cell library 5 and the standard cell library 6 for subsequent output of predetermined data according to information of the circuit diagram fetched from the RT circuit diagram input section 1a. The system also includes a datapath placement and routing section 12a for fetching both information of the circuit diagram from the RT circuit diagram input section 1a and data of the datapath section cells from the library reference section 7a for subsequent determinations of placements of the datapath section cells and interconnections between them to define a datapath section layout. The system also includes a datapath section layout file 13 for storing the layout of the datapath section determined by the datapath placement and routing section 12a. The system also has a standard cell placement and routing section 14b for fetching both the peripheral circuit/control system netlist from the peripheral circuit/control system netlist file 20a and information of the standard cells from the library reference section 7a for subsequent determinations of placements of the standard cells in the peripheral circuit and in the control system and interconnections between the standard cells to define a layout of the peripheral circuit/control system section. The system also has a peripheral circuit/control system layout file 21 for storing the peripheral circuit/control system layout determined by the standard cell placement and routing section 14b. The system also has a datapath section layout file 13 for storing the datapath section layout defined by the datapath placement and routing section 12a. The system also has a datapath circuit placement and routing section 16b for fetching the datapath Section layout from the datapath section layout file 13, the peripheral circuit/control system layout from the peripheral circuit/control system layout file 21 and information of the circuit diagram from the RT circuit diagram input section 1a for subsequent determinations of placements of the individual datapath section and the peripheral circuit/control systems and interconnections between them as well as interconnections of them to connective terminals to define the datapath circuit layout. The system also has an output section 17 for fetching the datapath circuit layout from the datapath circuit placement and routing section 16b for subsequent output thereof as a result 200a of the datapath circuit layout.
According to the foregoing conventional datapath circuit layout creation system, the layout of the datapath section is determined on the basis of the circuit diagram information and the data of the datapath section cells, while the layout of the peripheral circuit/control system is determined on the basis of the peripheral circuit/control system netlist and the data of the standard cells. Then, the layout of the datapath circuit is determined on the basis of the above both layouts of the datapath sections and the peripheral circuit/control system as well as the circuit diagram information.
The above described conventional datapath circuit layout creation system is engaged with a problem with difficulty in and time-consuming process in creation of the peripheral circuit/control system netlist. The difficulty and the time-consuming processes are caused by the coexisting of the peripheral circuits and the control systems, although the Coexisting thereof are actually required.
Another datapath circuit layout creation system has also been known in the art which will be described with reference to FIG. 4 in which the netlist includes only the peripheral circuit, but no control system. The process for determining the datapath section layout is the same as that of the above described conventional system, while a peripheral circuit function describe library 22 is created by referring to the RT circuit diagram 100 for determination of the peripheral circuit layout in a transistor level by a peripheral circuit generator 23 on the basis of the peripheral circuit functions stored in the peripheral circuit function describe library. A module routing section 24 fetches the peripheral circuit layout from the peripheral circuit layout file 15a, the datapath section layout from the datapath section layout file 13 and the RT circuit diagram information from the RT circuit diagram input section 1a for subsequent routing between the datapath section layout and the peripheral circuit layout on the basis of the circuit diagram to define the layout of the datapath circuit.
This other conventional system is also engaged with the following problem. The peripheral circuit generator 23 creates the peripheral circuit layout at the transistor level. It is then required to match the peripheral circuit layout to the cell level layout. This requires extra time. The creation of the peripheral circuit function describe library also takes a considerable amount of time.